1. Technical Field
The present invention relates to the reliability of integrated circuits, and more particularly to a method for estimating delay deterioration in integrated circuits due to device degradation.
2. Description of the Related Art
Very large scale integration (VLSI) circuits are designed and manufactured using imperfect processes and numerous tests must be run to check the functionality of a VLSI circuit. Such circuits degrade with use over time due to known and predictable effects such as bias temperature instability (BTI) and hot carrier injection (HCI). As a result, manufactured VLSI circuits are more likely to fail in the field, even though they have successfully passed numerous functional and verification tests prior to shipping.
The degradation of individual devices within a VLSI circuit may manifest itself as a change from nominal values established at the time production in one or more characteristics of a device. As an example, degradation may manifest itself as a change from the nominal value of a device's threshold-voltage or mobility.
A precise estimate of degradation in a VLSI circuit is nearly impossible due to such factors as highly complex designs, variations in manufacturing processes, multiple operating environments and approximations made during the modeling of these circuits. An over-estimation of a device's degradation may not take into account that device's ability to recover from the effects HCI and BTI degradation or that device's higher slope times which may compensate for degradation. As a result, excessive guardbands may be applied and good dies on which VLSI circuits may be formed are wasted. On the other hand, an under-estimation of a device's degradation may result in not fully testing certain critical pathways within a circuit. As a result, the eventual degradation of devices within a packaged integrated circuit may actually occur at a customer location even though the device passed functional and verification tests prior to shipping.